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cy7c1353g 4-mbit (256 k 18) flow-through sram with nobl? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05515 rev. *j revised september 25, 2012 4-mbit (256 k 18) flow-through sram with nobl? architecture features supports up to 100-mhz bus operations with zero wait states ? data is transferred on every clock pin compatible and functionally equivalent to zbt? devices internally self timed output buf fer control to eliminate the need to use oe registered inputs for flow-through operation byte write capability 256 k 18 common i/o architecture 2.5 v / 3.3 v i/o power supply (v ddq ) fast clock-to-output times ? 8.0 ns (for 100-mhz device) clock enable (cen ) pin to suspend operation synchronous self timed writes asynchronous output enable available in pb-free 100-pin tqfp package burst capability ? linear or interleaved burst order low standby power functional description the cy7c1353g is a 3.3 v, 256 k 18 synchronous flow-through burst sram designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. the cy7c1353g is equipped with the advanced no bus latency? (nob l?) logic requ ired to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the throughput of data through the sram, especially in systems that require frequent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the clock ri se is 8.0 ns (100-mhz device). write operations are controlled by the two byte write select (bw [a:b] ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state c ontrol. to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. c mode bw a bw b we ce 1 ce 2 ce 3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c clk cen write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control logic block diagram
cy7c1353g document number: 38-05515 rev. *j page 2 of 18 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 pin definitions .................................................................. 4 functional overview ........................................................ 5 single read accesses ................................................ 5 burst read accesses .................................................. 5 single write accesses ................................................. 5 burst write accesses .................................................. 5 sleep mode ................................................................. 6 linear burst address table ......................................... 6 interleaved burst address tabl e ................................. 6 zz mode electrical characteri stics .............................. 6 truth table ........................................................................ 7 partial truth table for read/write .................................. 7 maximum ratings ............................................................. 8 operating range ............................................................... 8 electrical characteristics ................................................. 8 capacitance ...................................................................... 9 thermal resistance .......................................................... 9 ac test loads and waveforms ....................................... 9 switching characteristics .............................................. 10 switching waveforms .................................................... 11 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 package diagram ............................................................ 14 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc solutions ......................................................... 18
cy7c1353g document number: 38-05515 rev. *j page 3 of 18 selection guide description 100 mhz unit maximum access time 8.0 ns maximum operating current 205 ma maximum cmos standby current 40 ma pin configuration figure 1. 100-pin tqfp (14 20 1.4 mm) pinout a a a a a1 a0 nc/288m nc/144m v ss v dd nc/36m a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe nc/18m a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a nc/9m adv/ld zz mode nc/72m cy7c1353g byte a byte b
cy7c1353g document number: 38-05515 rev. *j page 4 of 18 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the 256 k address locations . sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw [a:b] input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to in itiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld must be driven low to load a new address. clk input-clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 , and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/desel ect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. while deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critical ?sleep? condition with data integrity preserved. during normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, they deliver the da ta contained in the memory location specified by address during the clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq s and dqp [a:b] are placed in a tri-state condition. the outputs are automatically tri- stated during the data portion of a write sequence, during the first clock wh en emerging from a deselected state, and when the device is deselected, regar dless of the state of oe . dqp [a:b] i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq s . during write sequences, dqp [a:b] is controlled by bw x correspondingly. mode input strap pin mode input. selects the burst order of the device. when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device .
cy7c1353g document number: 38-05515 rev. *j page 5 of 18 functional overview the cy7c1353g is a synchronous flow-through burst sram designed specifically to eliminate wait states during write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 8.0 ns (100-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device is latched. the access can either be a read or write oper ation, depending on the status of the write enable (we ). bw [a:b] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipe lined. adv/ld must be driven low after the device has been deselected to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and 4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is av ailable within 8.0 ns (100-mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another operation (re ad/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output is tri-stated immediately. burst read accesses the cy7c1353g has an on-chip bu rst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low to load a new address into the sram, as described in the single read accesses section. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and wraps around when incremented sufficiently. a high input on adv/ld increments the internal burst counter regardless of the state of chip enable inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated when these conditions are satisfied at clock rise: cen is asserted low ce 1 , ce 2 , and ce 3 are all asserted active the write signal we is asserted low. the address presented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically tri-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp [a:b] . on the next clock rise the da ta presented to dqs and dqp [a:b] (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the wr ite operation is controlled by bw [a:b] signals. the cy7c1353g prov ides byte write capability that is described in the truth table. asserting the write enable input (we ) with the selected byte wr ite select input selectively writes to only the desired bytes. bytes not selected during a byte write operation remains unaltered. a synchronous self timed write mechanism has been provided to simplify the write operations. byte write capability has been included to greatly simplify read/modify/ write sequences, which can be reduced to simple byte write operations. because the cy7c1353g is a comm on i/o device, data must not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs and dqp [a:b] inputs. doing so tri-states the output drivers. as a safety precaution, dqs and dqp [a:b] .are automatically tri-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1353g has an on-chip bu rst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasse rting the address inputs. adv/ld nc, nc/9m, nc/18m, nc/36m, nc/72m, nc/144m, nc/288m ? no connects . not internally connected to the die. nc/9m, nc/18m, nc/72m , nc/144m, nc/288m, are address expansion pins are not internally connected to the die. pin definitions (continued) name i/o description
cy7c1353g document number: 38-05515 rev. *j page 6 of 18 must be driven low to load the initial address, as described in the single write accesses section. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw [a:b] inputs must be driven in each cycle of the burst write, to wr ite the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the o peration guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ?? 0.2 v ? 40 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ? ns
cy7c1353g document number: 38-05515 rev. *j page 7 of 18 truth table the truth table for cy7c1353g follows. [1, 2, 3, 4, 5, 6, 7] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tri-state deselect cycle none x x h l l x x x l l->h tri-state deselect cycle none x l x l l x x x l l->h tri-state continue deselect cycle none x x x l h x x x l l->h tri-state read cycle (begin burst) external l h l l l h x l l l->h data out (q) read cycle (continue burst) next x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tri-state dummy read (continue burst) next x x x l h x x h l l->h tri-state write cycle (begin burst) external l h l l l l l x l l->h data in (d) write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burst) none l h l l l l h x l l->h tri-state write abort (continue burst) next x x x l h x h x l l->h tri-state ignore clock edge (stall) current x x x l x x x x h l->h ? sleep mode none x x x h x x x x x x tri-state partial truth table for read/write the partial truth table for read/write for cy7c1353g follows. [1, 2, 8] function we bw a bw b read hxx write ? no bytes written lhh write byte a ? (dq a and dqp a )llh write byte b ? (dq b and dqp b )lhl write all bytes lll notes 1. x =?don?t care.? h = logic high, l = logic low. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 2. write is defined by bw x , and we . see truth table for read/write. 3. when a write cycle is detected, all ios are tri-stated, even during byte writes. 4. the dqs and dqp [a:b] pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. cen = h, inserts wait states. 6. device powers up deselected and the ios in a tri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp [a:b] = tri-state when oe is inactive or when the device is deselected, and dqs and dqp [a:b] = data when oe is active. 8. table only lists a partial listing of the byte write combinations. any combination of bw[a:d] is valid. appropriate write is based on which byte write is active.
cy7c1353g document number: 38-05515 rev. *j page 8 of 18 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.5 v to +4.6 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc voltage applied to outputs in tri-state ..........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................. ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, method 3015) ................................ > 2001 v latch-up current ................................................... > 200 ma operating range range ambient temperature (t a ) v dd v ddq commercial 0 c to +70 c 3.3 v ? 5% / + 10% 2.5 v ? 5% to v dd electrical characteristics over the operating range parameter [9, 10] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i oh = 8.0 ma ? 0.4 v for 2.5 v i/o, i oh = 1.0 ma ? 0.4 v v ih input high voltage for 3.3 v i/o 2.0 v dd + 0.3 v input high voltage for 2.5 v i/o 1.7 v dd + 0.3 v v il input low voltage [9] for 3.3 v i/o ?0.3 0.8 v input low voltage [9] for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ? 55a input current of mode input = v ss ?30 ? a input = v dd ?5a input current of zz input = v ss ?5 ? a input = v dd ?30a i oz output leakage current gnd ? v i ? v ddq , output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 10-ns cycle, 100 mhz ?205ma i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max , inputs switching 10-ns cycle, 100 mhz ?80ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static 10-ns cycle, 100 mhz ?40ma i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? v ddq ? 0.3 v or v in ? 0.3 v, f = f max , inputs switching 10-ns cycle, 100 mhz ?65ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static 10-ns cycle, 100 mhz ?45ma notes 9. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 10. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq ? v dd .
cy7c1353g document number: 38-05515 rev. *j page 9 of 18 capacitance parameter [11] description test conditions 100-pin tqfp max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v, v ddq = 3.3 v 5 pf c clock clock input capacitance 5pf c io i/o capacitance 5pf thermal resistance parameter [11] description test conditions 100-pin tqfp package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, according to eia/jesd51. 30.32 c/w ? jc thermal resistance (junction to case) 6.85 c/w ac test loads and waveforms figure 2. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load note 11. tested initially and after any design or proc ess changes that may affect these parameters.
cy7c1353g document number: 38-05515 rev. *j page 10 of 18 switching characteristics over the operating range parameter [12, 13] description -100 unit min max t power v dd (typical) to the first access [14] 1?ms clock t cyc clock cycle time 10 ? ns t ch clock high 4.0 ? ns t cl clock low 4.0 ? ns output times t cdv data output valid after clk rise ? 8.0 ns t doh data output hold after clk rise 2.0 ? ns t clz clock to low z [15, 16, 17] 0?ns t chz clock to high z [15, 16, 17] ?3.5ns t oev oe low to output valid ? 3.5 ns t oelz oe low to output low z [15, 16, 17] 0?ns t oehz oe high to output high z [15, 16, 17] ?3.5ns setup times t as address setup before clk rise 2.0 ? ns t als adv/ld setup before clk rise 2.0 ? ns t wes we , bw x setup before clk rise 2.0 ? ns t cens cen setup before clk rise 2.0 ? ns t ds data input setup before clk rise 2.0 ? ns t ces chip enable setup before clk rise 2.0 ? ns hold times t ah address hold after clk rise 0.5 ? ns t alh adv/ld hold after clk rise 0.5 ? ns t weh we , bw x hold after clk rise 0.5 ? ns t cenh cen hold after clk rise 0.5 ? ns t dh data input hold after clk rise 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? ns notes 12. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 13. test conditions shown in (a) of figure 2 on page 9 , unless otherwise noted. 14. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 15. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 2 on page 9 . transition is measured 200 mv from steady-state voltage. 16. at any voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus c ontention condition, but reflect parameters guaranteed over worst case user conditions . device is designed to achieve tri-state prior to low z under the same system conditions. 17. this parameter is sampled and not 100% tested.
cy7c1353g document number: 38-05515 rev. *j page 11 of 18 switching waveforms figure 3. read/write waveforms [18, 19, 20] write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw [a:b] adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq command t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz don?t care undefined d(a5) t doh q(a4+1) d(a7) q(a6) notes 18. for this waveform zz is tied low. 19. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 20. order of the burst sequence is determined by the status of the mode (0 = linear, 1 = interleaved). burst operations are opti onal.
cy7c1353g document number: 38-05515 rev. *j page 12 of 18 figure 4. nop, st all and deselect cycles [21, 22, 23] figure 5. zz mode timing [24, 25] switching waveforms (continued) read q(a3) 456 78910 a3 a4 a5 d(a4) 123 clk ce we cen bw [a:b] adv/ld address dq command write d(a4) stall write d(a1) read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a1 a2 q(a2) d(a1) q(a3) t doh q(a5) t zz i supply clk zz t zzrec all inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 21. for this waveform zz is tied low. 22. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 23. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a write is not performed during this cycle. 24. device must be deselected when entering zz mode. see truth ta ble for all possible signal conditions to deselect the device. 25. dqs are in high z when exiting zz sleep mode.
cy7c1353g document number: 38-05515 rev. *j page 13 of 18 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurations and feat ures. the following table contai ns only the list of parts that are currently available. for a complete listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 100 CY7C1353G-100AXC 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial temperature range: c = commercial pb-free package type: a = 100-pin tqfp speed grade: 100 mhz process technology: g ? 90 nm part identifier: 1353 = fl, 256 kb 18 (4 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c1353g-100 a c cy 7 x
cy7c1353g document number: 38-05515 rev. *j page 14 of 18 package diagram figure 6. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1353g document number: 38-05515 rev. *j page 15 of 18 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable cen clock enable eia electronic industries alliance i/o input/output jedec joint electron devices engineering council nobl no bus latency oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1353g document number: 38-05515 rev. *j page 16 of 18 document history page document title: cy7c1353g, 4-mbit (256 k 18) flow-through sram with nobl? architecture document number: 38-05515 rev. ecn no. issue date orig. of change description of change ** 224363 see ecn rkf new data sheet. *a 288431 see ecn vbl updated features (removed 66 mhz frequency related information). updated selection guide (removed 66 mhz frequency related information). updated electrical characteristics (removed 66 mhz frequency related information). updated switching characteristics (removed 66 mhz frequency related information). updated ordering information (updated part numbers (removed 66 mhz frequency related information, changed tqfp package in ordering information section to pb -free tqfp)). *b 333626 see ecn syt updated features (removed 117 mhz frequency related information). updated selection guide (removed 117 mhz frequency related information). updated pin configuration (modified address expansion balls in the pinouts for 100-pin tqfp packages according to jedec standards). updated pin definitions . updated functional overview (updated zz mode electrical characteristics (replaced ?snooze? with ?sleep?)). updated truth table (replaced ?snooze? with ?sleep?). updated electrical characteristics (updated test conditions of v ol, v oh parameters, removed 117 mhz frequency related information). updated thermal resistance (replaced values of ? ja and ? jc parameters from tbd to their respective values). updated switching characteristics (removed 117 mhz frequency related information). updated ordering information (by shading and unshading mpns according to availability). *c 418633 see ecn rxu changed status from preliminary to final. changed address of cypress semicondu ctor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (updated note 10 (modified test condition from v ddq < v dd to v ddq < v dd ), changed ?input load current except zz and mode? to ?input leakage current except zz and mode?). updated ordering information (updated part numbers, replaced package name column with package diagram in the ordering information table). updated package diagram (spec 51-85050 (changed revision from *a to *b)). *d 480124 see ecn vkn updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *e 1274724 see ecn vkn / aesa updated ordering information (corrected typo). *f 2896584 03/20/2010 njy updated ordering information (removed obsolete part numbers from ordering information table). updated package diagram . *g 3033272 09/19/2010 njy added ordering code definitions added acronyms and units of measure minor edits and updated in new template *h 3357006 08/29/2011 prit updated package diagram . updated in new template.
cy7c1353g document number: 38-05515 rev. *j page 17 of 18 *i 3619154 05/16/2012 prit updated features (removed 133 mhz frequency related information). updated functional description (removed the note ?for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com .? and its reference, removed 133 mhz frequency related information). updated selection guide (removed 133 mhz frequency related information). updated operating range (removed industrial temperature range). updated electrical characteristics (removed 133 mhz frequency related information). updated switching characteristics (removed 133 mhz frequency related information). replaced all instances of io with i/o across the document. *j 3754982 09/25/2012 prit no technical updates. completing sunset review. document history page (continued) document title: cy7c1353g, 4-mbit (256 k 18) flow-through sram with nobl? architecture document number: 38-05515 rev. ecn no. issue date orig. of change description of change
document number: 38-05515 rev. *j revised september 25, 2012 page 18 of 18 zbt is a trademark of integrated device technology, inc. nobl and no bus latency are trademarks of cypress semiconductor. all p roducts and company names mentioned in this document may be the trademarks of their respective holders. cy7c1353g ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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